As technology advances, and the dimensions of transistor devices continue to shrink, fabrication of semiconductors require more advanced manufacturing processes/equipment (fab) that may require additional investment by semiconductor manufacturers. For example, a fab producing 28 nm node devices would need to be updated for manufacturing devices in 20 or 14 nm nodes. Still, it would be advantageous for a semiconductor manufacturer to be able to produce smaller pitch devices without major investment in a current fab. A fab producing devices in 28 nm nodes may be utilized to produce devices, for example in 22 nm nodes, which can still offer benefits such as smaller and more efficient IC device.
FIG. 1 schematically illustrates an example circuit diagram of a bit cell with double patterned metal layer structures. As shown, bit cell 100 includes pass-gates 101a and 101b, inverters 102a and 102b, bit lines 103a and 103b, word lines 105a and 105b, and internal nodes 107a and 107b for configuring a latch with the two inverters that respectively include P-type metal-oxide-semiconductor (PMOS) 109a and PMOS 109b and n-type metal-oxide-semiconductor (NMOS) 111a and NMOS 111b. Each inverter is connected to its respective power line 113a or 113b, and ground line 115a or 115b. The internal node 107a is connected to the pass-gate 101a which is controlled by the word line 105a, and the internal node 107b is connected to the pass-gate 101b which is controlled by the word line 105b. 
One of the challenges in implementing smaller node technologies is in the area of lithography processes, which are utilized to print/pattern various layers of a circuit design onto a surface of a silicon (Si) substrate for creating devices (e.g., transistors) and circuits to form an IC device. Patterning smaller technology nodes in compact areas of an IC device can be difficult and time consuming. In some instances, a single patterning lithography process may be incompatible for defining a compact layer such as a metal1 (M1) layer in a memory bit cell, where the M1 layer may be limited to be printed on a Si substrate below metal pitch 90 nm including a line width of 45 nm and spacing of 45 nm.
FIG. 2A illustrates an example layout diagram of a SRAM cell with single patterned metal layer structures. In this example, the layout is for a typical SRAM memory cell that includes M1 word line structure as landing pads 201, M1 ground line structure as landing pads 203, M1 bit line structure 205, and metal2 (M2) layer structure 207. In addition, the layout includes active region contacts 209, metal contacts 211, and vial structures 213 to provide various interconnections for the M1 layer structures 201, 203, and 205, and the M2 layer structure 207. However, this layout may be difficult to print onto a substrate as the metal structures may be too close to each other to be printed by the same patterning process. As shown, for instance, word line landing pads 201 may be too close to ground line landing pads 203, and landing pads 201 and 203 may be too close to bit line structure 205. As such, it may become increasingly difficult to further shrink the design of the memory cell.
Illustrated in FIG. 2B is another example of a memory cell layout including single patterned metal lines (e.g., M1 layer structures 215 and 217) that could occupy a significant space in an IC device. However, if the height of the memory cell is reduced (e.g., to decrease the space occupied), the tip-to-tip spacing between the M1 layer structures 217 (in which the tip is narrower side of the structure), particularly when patterned by a single patterning process, will become too close, negatively affecting lithographic printability and reliability. However, a more advanced lithographic process of double patterning may address some of the challenges as discussed.
FIGS. 3A and 3B illustrate example layout diagrams of a memory cell utilizing a double patterning lithography process. In double patterning, litho-etch-litho-etch, litho-freeze-litho-etch, self-aligned-double-patterning, or the like processes may be utilized.
FIG. 3A illustrates local interconnection layers and via0 structures. A memory cell 300 (e.g., one of the memory cells in a 2-by-2 array) includes via0 structures 301 for connecting metal layer structures to active region contacts (not shown for illustrative convenience). Local interconnection layer (or active contact region) 303 is connected to via0 contact region 301, and another local interconnection layer 305 for connecting internal nodes with poly contact region 307, which is connected to poly gate region (not shown for illustrative convenience). Another poly contact region 309 is shown to contact to a poly gate for word line (not shown for illustrative convenience). These local interconnection layers allow flexibility in placement of via0 contacts for connecting to the M1 layer. With local interconnection layers, an active contact layer is single patterned, so that internal nodes are positioned as tip-to-tip, e.g., the active contact region 305 and another active region 305a. Also, a poly contact region is single patterned such that the poly contact region 307 is positioned tip-to-tip with adjacent poly contact region 307a in a next cell.
FIG. 3B illustrates M1 layer structures and vial structures associated with FIG. 3A. As shown in FIG. 3B, local interconnection layers are not directly connected to M1 layer, so that there is flexibility in forming the shape of the M1 layers for contact with the via0 structures 301. M1 layer structures of the cell 300 in FIG. 3A include M1 ground line structures 311a and 311b, M1 word line structures 313a and 313b, M1 power line structure 315, and M1 bit line structures 317a and 317b. In a double patterning process, bit line structures 317a and 317b are by a first patterning process and the other structures are by a second patterning process. With local interconnect layers 303 and 309 in FIG. 3A, a repeating array may be configured without complexity since the cell in FIG. 3B includes symmetrical metal layers.
In more advanced technology nodes (e.g., 20 nm and below), middle of lines are used for connecting nodes as local interconnections. A local interconnection layer may be added under a via0 layer, which may be formed under M1 layer. However, local interconnection layers require additional mask layers, which would increase manufacturing cost and time.
Therefore, a need exists for a miniaturized bit cell, without local interconnection layers, with improved lithographic printability, and enabling methodology.